The invention relates to the field of semiconductors and more particularly to MOS transistors. It especially applies to power MOS transistors.
More particularly, the invention relates to a composite MOS transistor, the substrate of which is automatically connected to the lowest of the potentials applied to its two main electrodes (source and drain).
On the other hand, the invention relates to an application of the component according to the invention to a free-wheel diode structure, of the active diode type, that can be made in monolithic form on a chip also comprising a power MOS transistor of the vertical diffused MOS (VDMOS) type, or equivalent.
Before describing the invention, the problems encountered for implementing a free-wheel diode in technologies using vertical diffused MOS transistors and lateral logic MOS transistors on the same integrated circuit chip are described.
First, FIG. 1 shows the connection of a power switch 1 and a load 2 across a d.c. supply 3. Conventionally, in case load 2 is an inductive load, a diode 4, called free-wheeling diode, is connected in series with the power switch and in parallel with the load; this diode is designed to let the inductive current of the load flow when the switch is switched off, and is reverse biased with respect to the current flow direction when the main switch 1 is switched on. The free-wheel diode prevents substantial overvoltages when the main switch 1 in series with the load abruptly switches off.
The users of power switch generally wish to have this free-wheel diode 4 integrated in the same semiconductive chip as the power switch.
FIG. 2 is a very schematic section view of such a free-wheel diode integrated on the same chip as a VDMOS and transistors forming a control circuit.
As shown on FIG. 2, this technology uses a substrate comprising an N.sup.+ -type lower layer 10 and an N-type layer 11. In the N-type layer 11 are formed numerous cells of the power MOS transistor, one of which is schematically shown and referenced 12. Each cell of the power transistor comprises P diffusion areas 13 wherein N areas 14 are diffused. A source metallization 15 contacts the areas 14 and the P area 13 which separates them. A gate metallization (polysilicon) 16 permits opening of the channels in the lateral portions of the P areas so that a conduction path is established between the source electrode 15 and a drain metallization 17 formed on the rear surface of the component.
There are also in this structure one or several P-type well(s) 20 wherein are formed MOS transistors 21 permitting a control circuit to be made.
A conventional method for realizing a monolithic free-wheel diode consists in carrying out in a P-type well 30, analogous to the wells 20 comprising the control circuits, an N.sup.+ diffusion 31 and a P.sup.+ contact 32, associated with metallizations 33 and 34, respectively. Metallization 33 is connected to the source metallization 15 and to the first load terminal and metallization 34 is connected to the other load terminal and to the negative terminal of the supply source 3, the positive terminal of which is connected to drain D.
The equivalent circuit diagram of FIG. 2 is illustrated in FIG. 3, wherein load 2, current source 3 and power transistor 12 are shown again. The N.sup.+ junction P between areas 31 and 32 corresponds to the emitter-base junction of a NPN-type parasitic bipolar transistor 35, the collector of which corresponds to layers 11 and 10 of FIG. 2 and is consequently connected to the drain D of the power transistor 12. As a result, during the free-wheel diode operation, a substantial power dissipation occurs in that parasitic transistor 35 and the parasitic currents may impair the control circuits. The conventional methods for reducing the gain of this parasitic bipolar transistor are inadequate due to the high current liable to flow through the load.
To palliate this drawback, it has been devised in prior art to realize structures of the "active diode" type, that is, controlled structures, selectively conductive or non-conductive according to the polarity of the voltage across their terminals.
Such an active diode structure is illustrated on FIG. 4. It comprises the same components labelled with the same references as those of FIG. 3 with the addition of a MOS transistor 40 in parallel with load 2 controlled in opposition with respect to power transistor 12. Thus, this transistor 40 is blocked when transistor 12 is conductive, and conductive when transistor 12 is blocked.
This method seems a prori satisfactory; however, in the structures of the above described type, there remains a parasitic bipolar transistor 35. Indeed, transistor 40 is for example made in the way illustrated in FIG. 5: it is formed in a well 41 analogous to well 30 of FIG. 2 and comprises a drain area 42 and a source area 43 connected by a metallization to a P.sup.+ -type overdoped area 44 establishing a contact with well 41. A gate is provided between the drain and source regions. Load 2 is connected between the metallizations of drain 45 and of source 46. As in FIG. 2, the drain metallization 45 will be connected to the source 15 of the power transistor. However, as shown in FIG. 4, there remains a parasitic transistor 35, the emitter of which corresponds to region 42, the base to the well 41 and the collector to the power transistor drain. Normally, this parasitic bipolar transistor 35 is inactive when MOS transistor 40 is conductive (during the free-wheel operation). However, to enable transistor 35 to remain blocked, the voltage drop across the terminals of transistor 40 has to be lower than the emitter/base voltage drop of a bipolar transistor, that is, about 0.7 volt. This implies a low resistor at the conductive state of the MOS transistor 40 and therefore a substantial surface thereof, which one tries to avoid in the realization of a component.
Thus, the two solutions of the prior art, respectively shown in FIGS. 2 and 5, cause the presence of a parasitic bipolar transistor, the effects of which are damaging except, in case of FIGS. 4 and 5, if one chooses to lose a large silicon surface.
Moreover, in both cases according to the above mentioned prior art, during the free-wheeling operation, it is not possible to rapidly dampen the current, the latter being limited only by the internal resistance of the load which is often very weak. Indeed, even in case of FIGS. 4 and 5, if the resistance of the MOS transistor 40 is increased, this causes conduction of the base/emitter diode of the bipolar transistor 35, and therefore the switching of this transistor into the conductive state.
Lastly, another drawback of those arrangements according to the prior art lies in the fact that, in case of an accidental polarity reversal of the current source (which is a non negligible risk for example in case of a circuit connected to a car battery), the current is not limited in any way and can flow through the free-wheel diode and through the diode existing inherently in parallel on the power transistor 12 (this diode is connected between the metallization of drain 17 and of source 15 which is also in contact with the P-type region 13 (see FIG. 2)).